VMIPCI-5565 Ultrahigh Speed Fiber-Optic Reflective Memory

Product Overview: The Reflective Memory concept provides a
very fast and efficient way of sharing data across distributed
computer systems.
The VMIPCI-5565 Reflective Memory interface allows data to be
shared between up to 256 independent systems (nodes) at rates
up to 174MB/s. Each Reflective Memory board may be
configured with 64MB or 128MB of onboard SDRAM. The local
SDRAM provides fast Read access times to stored data. Writes
are stored in local SDRAM and broadcast over a high speed
fiber-optic data path to other Reflective Memory nodes. The
transfer of data between nodes is software transparent, so no
I/O overhead is required. Transmit and Receive FIFOs buffer
data during peak data rates to optimize the host computer and
bus performance to maintain high data throughput.
The Reflective Memory also allows interrupts to one or more
nodes by writing to a byte register. These interrupt (four levels,
each user definable) signals may be used to synchronize a
system process, or used to follow any data. The interrupt always
follows the data to ensure the reception of the data before the
interrupt is acknowledged.

VMIPCI-5565-110000

Each node on the system has a unique identification number
between 0 and 255. The node number is established during
hardware system integration by placement of jumpers on the
board. This node number can be read by software by accessing
an onboard register. In some applications, this node number
would be useful in establishing the function of the node.
Link Arbitration: The VMIPCI-5565 system is a fiber-optic daisy
chain ring as shown in Figure 2. Each transfer is passed from
node-to-node until it has gone all the way around the ring and
reaches the originating node. Each node retransmits all
transfers that it receives except those that it originated. Nodes
are allowed to insert transfers between transfers passing
through.
Interrupt Transfers: The VMIPCI-5565 provides four network
interrupts. Any processor can generate an interrupt on any
other node on the network. In addition, any processor can
generate an interrupt on all nodes on the network with a single
register write.