中文版
Description
3008N MAIN PROCESSOR MODULESThe Tricon V10 main processor subsystem utilizes three 3008N MP modules to control the three separate legs of the system. Each 3008N MP module operates independently with no shared clocks, power regulators, or circuitry. Each 3008N MP module controls one of the three signal processing legs in the system and each contains two 32-bit processors. One of the 32-bit processors is a dedicated, leg-specific I/O and communication (IOCCOM) microprocessor that processes all communication with the system I/O modules and communication modules. The second 32-bit primary processor manages execution of the safety control program and all system diagnostics at the main processor module level. Between thetwo 32-bit primary processors is a dedicated dual port random access memory (RAM) allowing for direct memory access data exchanges. The operating system (ETSX 6271), run-time library, and fault analysis for the main processor is fully contained in flash memory on each 3008N MP module. As shown in Figure 3-2, the Tricon V10 PLC system has four separate bus structures, the Tribus, the communications bus, the I/O bus, and the bus internal to each of the main processor modules. Each of these bus structures is triplicated. The main processors communicate with one another through a proprietary, high speed, voting, bi-directional serial channel called TriBUS. Each main processor has an I/O channel for communicating with one of the three legs of each I/O module. All external data coming into the main processor comes through the dual port RAM and does not require handshaking or use of interrupts. Each main processor has an independent clock circuit and selection mechanism that enables all three main processors to coordinate their operations each scan to allow voting of data and exchange of diagnostic information.
TRICONEX 3008N
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