VMIVME-5576 Fiber-Optic Reflective Memory with Interrupts

Features:
  • High-Speed Fiber Optic Network
  • 2000 m Between Nodes, Up to 256 Nodes
  • Error Detection
  • Redundant Transmission Mode for Suppressing Errors
  • A24:A32:D32:D16:D8 Memory Access

The VMIC / GE Fanuc VMIVME-5576 Reflective Memory interface allows data to be shared

between up to 256 independent systems (nodes) at rates up to 6.2 Mbyte/s. Each Reflective Memory

board may be configured with 256 Kbyte to 1 Mbyte of on-board SRAM. The local SRAM provides

fast Read access times to stored data.

Category:

Description

VMIVME-5576 Fiber-Optic Reflective Memory with Interrupts

Features:
  • High-Speed Fiber Optic Network
  • 2000 m Between Nodes, Up to 256 Nodes
  • Error Detection
  • Redundant Transmission Mode for Suppressing Errors
  • A24:A32:D32:D16:D8 Memory Access

The VMIC / GE Fanuc VMIVME-5576 Reflective Memory interface allows data to be shared

between up to 256 independent systems (nodes) at rates up to 6.2 Mbyte/s. Each Reflective Memory

board may be configured with 256 Kbyte to 1 Mbyte of on-board SRAM. The local SRAM provides

fast Read access times to stored data. Writes are stored in local SRAM and broadcast over a high-speed

fiber-optic data path to other Reflective Memory nodes.

VMIVME-5576

The transfer of data between nodes is

software transparent, so no I/O overhead is required. Transmit and Receive FIFOs buffer data

during peak data rates to optimize CPU and bus performance to maintain high data throughput.

The Reflective Memory also allows interrupts to one or more nodes by writing to a byte register.

These interrupt (three level, user definable) signals may be used to synchronize a system process,

or used to follow any data that may have preceded it. The interrupt always follows the data to

ensure the reception of the data before the interrupt is acknowledged. The VMIVME-5576 requires no

initialization unless interrupts are being used. If interrupts are used, vectors and interrupt levels must be written to on-board registers and the interrupts armed.

Each node on the system has a unique identification number between 0 and 255. The node number is

established during hardware system integration by placement of jumpers on the board. This node

number can be read by software by accessing an on-board register. In some applications, this node number would be useful in establishing the function of the node.

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